1. Field of the Invention
The present invention generally relates to non-volatile random access memory (NVRAM) arrays and, more particularly, to arrays of memory cells formed as a field effect transistor having a floating gate on which charge can be placed by tunnelling effects.
2. Description of the Prior Art
Digital signal processing arrangements such as microprocessors use many different types of memory and storage structures for different purposes. The type of memory used will often be determined by the needed speed of access, the length of time data will be stored and the operational circumstances during storage of data. For example, a read-only memory (ROM) is used for data which is necessary for operation of the processor and never changed while a random access memory (RAM) of either a static or dynamic type is used for the working memory of the processor and access speed may be enhanced by the use of one or more levels of caching. In general, random access memories can only store data when power is applied thereto.
Between these extremes, various storage structures are known for storage of data which may be changed at will but under circumstances where power is not or cannot be maintained at all times during data storage. Various magnetic media such as well-known hard disks are often used for such purposes. However, magnetic storage devices rely on relative movement between the storage medium and a reading device in order to write and erase data on the medium and the mechanical arrangement for doing so is subject to wear, damage or malfunctions and is a source of potential damage to the storage medium, as well. The mechanical arrangement also imposes a lower limit on size and weight of the storage device.
It is generally considered that semiconductor arrangements would provide increased reliability, reduced susceptibility to damage and potentially reduced size and weight to perform the non-volatile storage functions for which magnetic media are now generally used. Electrically erasable programmable read only memories (EEPROMs) are known which generally employ memory cells which are similar to a field effect transistor but include an additional insulated structure referred to as a floating gate on which charge can be selectively stored. The charge can be placed on or removed from the floating gate by several known tunnelling effects such as Fowler-Nordheim tunnelling or channel hot electron tunnelling. When a potential is placed on an electrode known as a control gate located over the floating gate, the channel of the transistor will become conductive or not depending on the total electric field contributions of the control gate and the charge, if any, on the floating gate.
In order to create a viable semiconductor alternative to magnetic media, significant development has been required in three principal areas of performance: memory cell capacity of a single chip, the number of write and erase cycles which can be reliably performed and the required cycle time for write and erase operations. In this regard, recent developments in cell layout and lithographic and semiconductor manufacturing process have allowed several millions of storage cells to be placed on a single chip of substantially standard dimensions and storage capacity of a single package has been further increased by multi-chip modular packaging. Similarly, while each write and erase cycle causes slight but cumulative damage to the insulation surrounding the floating gate, improvements in insulator materials and operating techniques have provided sufficient numbers of write and erase cycles to assure reliable operation over a period of time well in excess of the period of obsolescence of processors in many applications.
However, since tunnelling currents are very small, the write and erase cycle times have remained relatively intractable, consistent with reliability and small cell size. Reduced thickness of floating gate insulation can reduce the needed amount of stored charge but increases susceptibility to damage by tunnelling currents and increasing leakage with use as well as possibly compromising manufacturing yield. For a given thickness of floating gate insulator, reduced stored charge corresponds to reduced operating margins and increased possibility of read errors. Likewise, increase of tunnelling current by operation at increased write and erase voltages also increases the likelihood of insulator damage.
In general, the necessary amount of stored charge and available tunnelling current are such that write and erase times are several orders of magnitude longer than those of static or dynamic RAMs and erase cycle times may be in the millisecond range. Such cycle times certainly do not compare favorably with the bandwidth of current magnetic media. No significant reduction in write and erase cycle times has been achieved that does not compromise cell size, operating margins, reliability and/or manufacturing yield.
It is therefore an object of the present invention to provide a non-volatile memory structure with reduced write and erase cycle times.
It is another object of the invention to provide increased write and erase tunnelling current in a non-volatile semiconductor memory device without compromising cell size, operating margins, reliability or manufacturing yield.
It is a further object of the invention to provide a non-volatile memory cell structure in which increased tunnelling current is achieved at a given write or erase voltage.
In order to accomplish these and other objects of the invention, a non-volatile memory cell and an integrated circuit such as a non-volatile memory array are provided in which the non-volatile memory cell includes a semiconductor substrate having an edge structure including oppositely directed edges formed in a gate area and providing enhancement of an electric field adjacent a floating gate which is insulated from the substrate, and a control gate located adjacent but insulated from the floating gate within said gate area.
In accordance with another aspect of the invention, a method of forming a non-volatile memory cell on a monocrystalline semiconductor substrate is provided including steps of applying an apertured mask to the substrate wherein the mask includes a mask element separating one aperture region from another aperture region, and preferentially etching the monocrystalline substrate in directions to form edges directed away from and toward a floating gate.